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SEMICONDUCTOR TECHNICAL DATA
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TMOS E-FET.TM Power Field Effect Transistor DPAK for Surface Mount
N-Channel Enhancement-Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications such as power supplies, PWM motor controls and other inductive loads, the avalanche energy capability specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified at Elevated Temperature * Low Stored Gate Charge for Efficient Switching * Internal Source-to-Drain Diode Designed to Replace External Zener Transient Suppressor - Absorbs High Energy in the Avalanche Mode * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode G * Surface Mount Package Available in 16 mm, 13-inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number * Available in Insertion Mount, Add -1 or 1 to Part Number MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage -- Continuous Gate-to-Source Voltage -- Single Pulse (tp 50 S) Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 S) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C when mounted with the minimum recommended pad size Operating and Storage Temperature Range
MTD14N10E
Motorola Preferred Device
TMOS POWER FET 14 AMPERES 100 VOLTS RDS(on) = 0.14 W
(R)
D CASE 369A-13, Style 2 DPAK
S
Symbol VDSS VDGR VGS VGSM ID ID IDM PD
Value 100 100 20 25 14 10 49 72 0.58 1.75 - 55 to 150
Unit Vdc Vdc Vdc Vdc Adc Apk Watts W/C Watts C
TJ, Tstg
UNCLAMPED DRAIN-TO-SOURCE AVALANCHE CHARACTERISTICS (TJ < 150C)
Single Pulse Drain-to-Source Avalanche Energy -- STARTING TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, PEAK IL = 14 Apk, L = 1.0 mH, RG = 25 ) EAS 98 mJ
THERMAL CHARACTERISTICS
Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Thermal Resistance -- Junction to Ambient (1) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds (1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
RJC RJA RJA TL
1.73 100 71.4 260
C/W
C
E-FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
(c) Motorola TMOS Motorola, Inc. 1998
Power MOSFET Transistor Device Data
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MTD14N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 8.0 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 14 Adc) (VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge ( (VDS = 80 Vd , ID = 14 Adc, Vdc, Ad , VGS = 10 Vdc) Vdc, (VDS = 50 Vd ID = 14 Adc, Ad VGS = 10 Vdc Vdc, RG = 9.1 ) ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 14 Adc, VGS = 0 Vdc) (IS = 14 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr ( (IS = 14 Adc, Ad , dIS/dt = 100 A/s) Reverse Recovery Stored Charge (1) Pulse Test: Pulse Width 300 S, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. Max limit - Typ (3) Reflects typical values. Cpk 3 sigma ta tb QRR -- -- -- -- 0.92 0.80 103 78 25 0.46 1.5 -- -- -- -- -- C nS Vdc -- -- -- -- -- -- -- -- 9.0 58 26 33 26 5.0 13 11 20 120 50 70 40 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vdc Vdc f = 1.0 MHz) Ciss Coss Crss -- -- -- 700 200 65 980 280 130 pF Cpk 2.0(3) VGS(th) 2.0 -- Cpk 2.0(3) RDS(on) -- VDS(on) -- -- gFS 4.0 -- -- 7.4 1.85 1.62 -- mhos 0.098 0.14 Vdc 2.9 6.2 4.0 -- Vdc mV/C Ohms Cpk 1.5(3) V(BR)DSS 100 -- IDSS -- -- IGSS -- -- -- -- 10 100 100 nAdc -- 112 -- -- Vdc V/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time
+
2
Motorola TMOS Power MOSFET Transistor Device Data
MTD14N10E
TYPICAL ELECTRICAL CHARACTERISTICS
30 I D , DRAIN CURRENT (AMPS) 25 20 15 10 5 0 0 1 3 5 7 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 9 10 5V VGS = 10 V 9V 8V I D , DRAIN CURRENT (AMPS) 7V TJ = 25C 30 25 25C 20 15 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8.5 9 100C VDS 10 V
TJ = -55C
6V
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 ID, DRAIN CURRENT (AMPS) - 55C 25C VGS = 10 V TJ = 100C
0.14 0.13 0.12 0.11 0.10 15 V 0.09 0.08 0.07 0.06 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 ID, DRAIN CURRENT (AMPS) VGS = 10 V TJ = 25C
Figure 3. On-Resistance versus Drain Current and Temperature
1000 VGS = 10 V ID = 8 A I DSS , LEAKAGE (nA) 100
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50
VGS = 0 V TJ = 125C
100C
10
1 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 0 10 20 30 40 50 60 70 80 90 100 110 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
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MTD14N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
2200 2000 1800 C, CAPACITANCE (pF) 1600 1400
Ciss VDS = 0 V
VGS = 0 V
TJ = 25C
1200 Crss 1000 800 600 400 200 0 10 Crss 5 VGS 0 VDS 5 10 15 20
Ciss
Coss
25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTD14N10E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 2.5 Q3 5 VDS 7.5 10 12.5 15 17.5 20 QG, TOTAL GATE CHARGE (nC) TJ = 25C ID = 14 A 22.5 Q1 Q2 QT VGS 80 72 64 56 48 40 32 24 16 8 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 14 A VDD = 50 V VGS = 10 V tr tf td(off) 10 td(on)
0 25 27.5
t, TIME (ns)
100
1
1
10 RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
14 12 I S , SOURCE CURRENT (AMPS) 10 8 6 4 2 0 0.6 0.8 0.65 0.7 0.75 0.85 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 0.95 VGS = 0 V TJ = 25C
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
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MTD14N10E
SAFE OPERATING AREA
100 E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 100 s 1 ms 10 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 100 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 dc 10 s 110 100 90 80 70 60 50 40 30 20 10 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 ID = 14 A
0.1
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
t2 DUTY CYCLE, D = t1/t2 1.0E-03 t, TIME (s) 1.0E-02
1.0E-04
1.0E-01
1.0E+00
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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Motorola TMOS Power MOSFET Transistor Device Data
MTD14N10E
PACKAGE DIMENSIONS
-T- B V R
4
SEATING PLANE
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 --- 0.030 0.050 0.138 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 --- 0.77 1.27 3.51 ---
S
1 2 3
A K F L D G
2 PL
Z U
J H 0.13 (0.005) T
STYLE 2: PIN 1. 2. 3. 4. M
GATE DRAIN SOURCE DRAIN
DIM A B C D E F G H J K L R S U V Z
CASE 369A-13 ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
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MTD14N10E
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Motorola TMOS Power MOSFET Transistor MTD14N10E/D Device Data

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